In various applications, the output data from a number of circuit blocks are interleaved to provide an output data sequence. For example, multiple analog-to-digital converters (ADCs) or other types of processing units may operate in parallel, thereby increasing the data processing capacity of the system and the data rate of the output data.
Each of the parallel circuit blocks is for example controlled based on a master clock signal, and the outputs of the circuit blocks can be interleaved by assigning one clock cycle of the master clock signal to each of the circuit blocks in turn for outputting data. With an objective of further increasing the throughput of such systems, there is a trend for using increasingly higher master clock frequencies, for example over 1 GHz, and as high as 10 GHz or more.
There is a problem in synchronizing the output data from each of the circuit blocks by a synchronization block. Indeed, due to a difference in the time delay between the master clock and the clock signal present at each of the circuit blocks and the clock signal present at the synchronization block, it is generally not adequate to use the master clock signal to directly clock the synchronization block. Furthermore, at relatively high frequencies of the master clock signal, there is a problem in determining the correct delay to be applied to the master clock that is suitable for synchronizing the data.